TY - GEN
T1 - ZombieNAND
T2 - 2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014
AU - Wilson, Ellis H.
AU - Jung, Myoungsoo
AU - Kandemir, Mahmut T.
PY - 2015/2/5
Y1 - 2015/2/5
N2 - As consumer pressure for more bits per dollar and higher density-per-solid-state disk (SSD) forces manufacturers to squeeze more than one bit per flash cell and feature sizes downwards, wear-out is again becoming an increasing concern. Specifically, while single-level cell flash at larger feature sizes used to boast over 100,000 program/erase (P/E) cycles, modern triple-level cell flash can only sustain a measly 3,000 P/E cycles before it can no longer be reliably used. However, one lesser known facet of NAND flash design is that there is no material difference between cells that store one, two, or three bits per cell - it is merely a logical interpretation of the cells contents. Therefore, in this work we leverage this interesting property to explore how resurrecting dead flash cells to create 'Zombie-NAND' flash can improve an SSD's lifetime, and what, if any, impact on latency results in doing such. Specifically, we analyze the impact of switching a TLC or MLC cell down one bit upon death, this allows the voltage thresholds to rise and life, though at a lower capacity, to continue for that cell. Finding that traditional wear-leveling techniques actually inhibit the benefits of this scheme, we propose and explore how controlled 'wear-unleveling' can work in tandem with Zombie-NAND cells to provide vastly increased life and decreased latencies for the drive. In this exploration, we perform rigorous performance measurement over a number of parameters representative of a variety of commodity and commercial SSDs.
AB - As consumer pressure for more bits per dollar and higher density-per-solid-state disk (SSD) forces manufacturers to squeeze more than one bit per flash cell and feature sizes downwards, wear-out is again becoming an increasing concern. Specifically, while single-level cell flash at larger feature sizes used to boast over 100,000 program/erase (P/E) cycles, modern triple-level cell flash can only sustain a measly 3,000 P/E cycles before it can no longer be reliably used. However, one lesser known facet of NAND flash design is that there is no material difference between cells that store one, two, or three bits per cell - it is merely a logical interpretation of the cells contents. Therefore, in this work we leverage this interesting property to explore how resurrecting dead flash cells to create 'Zombie-NAND' flash can improve an SSD's lifetime, and what, if any, impact on latency results in doing such. Specifically, we analyze the impact of switching a TLC or MLC cell down one bit upon death, this allows the voltage thresholds to rise and life, though at a lower capacity, to continue for that cell. Finding that traditional wear-leveling techniques actually inhibit the benefits of this scheme, we propose and explore how controlled 'wear-unleveling' can work in tandem with Zombie-NAND cells to provide vastly increased life and decreased latencies for the drive. In this exploration, we perform rigorous performance measurement over a number of parameters representative of a variety of commodity and commercial SSDs.
UR - http://www.scopus.com/inward/record.url?scp=84937894022&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937894022&partnerID=8YFLogxK
U2 - 10.1109/MASCOTS.2014.37
DO - 10.1109/MASCOTS.2014.37
M3 - Conference contribution
T3 - Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS
SP - 229
EP - 238
BT - Proceedings - 2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014
PB - IEEE Computer Society
Y2 - 9 September 2014 through 11 September 2014
ER -