Worst case execution time analysis for synthesized hardware

Jun Hee Yoo; Xingguang Feng; Kiyoung Choi; Eui Young Chung; Kyu Myung Choi

doi:10.1145/1118299.1118503

Worst case execution time analysis for synthesized hardware

Jun Hee Yoo, Xingguang Feng, Kiyoung Choi, Eui Young Chung, Kyu Myung Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2006
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2006
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	905-910
Number of pages	6
ISBN (Print)	0780394518, 9780780394513
DOIs	https://doi.org/10.1145/1118299.1118503
Publication status	Published - 2006
Event	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan Duration: 2006 Jan 24 → 2006 Jan 27

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2006

Other

Other	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Country/Territory	Japan
City	Yokohama
Period	06/1/24 → 06/1/27

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1145/1118299.1118503

Cite this

Yoo, J. H., Feng, X., Choi, K., Chung, E. Y., & Choi, K. M. (2006). Worst case execution time analysis for synthesized hardware. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 905-910). Article 1594801 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1118299.1118503

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title = "Worst case execution time analysis for synthesized hardware",

abstract = "We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.",

author = "Yoo, {Jun Hee} and Xingguang Feng and Kiyoung Choi and Chung, {Eui Young} and Choi, {Kyu Myung}",

year = "2006",

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language = "English",

isbn = "0780394518",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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note = "ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 ; Conference date: 24-01-2006 Through 27-01-2006",

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Yoo, JH, Feng, X, Choi, K, Chung, EY & Choi, KM 2006, Worst case execution time analysis for synthesized hardware. in Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006., 1594801, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2006, Institute of Electrical and Electronics Engineers Inc., pp. 905-910, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 06/1/24. https://doi.org/10.1145/1118299.1118503

Worst case execution time analysis for synthesized hardware. / Yoo, Jun Hee; Feng, Xingguang; Choi, Kiyoung et al.
Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. p. 905-910 1594801 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.

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Yoo JH, Feng X, Choi K, Chung EY, Choi KM. Worst case execution time analysis for synthesized hardware. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc. 2006. p. 905-910. 1594801. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1118299.1118503

Worst case execution time analysis for synthesized hardware

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All Science Journal Classification (ASJC) codes

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