WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

Junyoung Ko; Younghwi Yang; Seong Ook Jung; Jisu Kim; Cheon An Lee; Young Sun Min; Jinyoung Chun; Moosung Kim

doi:10.1109/ISCAS.2016.7527417

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

Junyoung Ko, Younghwi Yang, Seong Ook Jung, Jisu Kim, Cheon An Lee, Young Sun Min, Jinyoung Chun, Moosung Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1022-1025
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527417
Publication status	Published - 2016 Jul 29
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 2016 May 22 → 2016 May 25

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Other

Other	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	16/5/22 → 16/5/25

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7527417

Cite this

Ko, J., Yang, Y., Jung, S. O., Kim, J., Lee, C. A., Min, Y. S., Chun, J., & Kim, M. (2016). WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 1022-1025). Article 7527417 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527417

Ko, Junyoung ; Yang, Younghwi ; Jung, Seong Ook et al. / WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 1022-1025 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{fab9cae94aeb471b8d571e443776484d,

title = "WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory",

abstract = "In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.",

keywords = "ISPP method, NAND Flash, Under-driving scheme, WL driving mehtod, WL driving scheme",

author = "Junyoung Ko and Younghwi Yang and Jung, {Seong Ook} and Jisu Kim and Lee, {Cheon An} and Min, {Young Sun} and Jinyoung Chun and Moosung Kim",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",

year = "2016",

month = jul,

day = "29",

doi = "10.1109/ISCAS.2016.7527417",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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Ko, J, Yang, Y, Jung, SO, Kim, J, Lee, CA, Min, YS, Chun, J & Kim, M 2016, WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527417, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 1022-1025, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 16/5/22. https://doi.org/10.1109/ISCAS.2016.7527417

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. / Ko, Junyoung; Yang, Younghwi; Jung, Seong Ook et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1022-1025 7527417 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

AU - Ko, Junyoung

AU - Yang, Younghwi

AU - Jung, Seong Ook

AU - Kim, Jisu

AU - Lee, Cheon An

AU - Min, Young Sun

AU - Chun, Jinyoung

AU - Kim, Moosung

PY - 2016/7/29

Y1 - 2016/7/29

N2 - In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

AB - In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

KW - ISPP method

KW - NAND Flash

KW - Under-driving scheme

KW - WL driving mehtod

KW - WL driving scheme

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DO - 10.1109/ISCAS.2016.7527417

M3 - Conference contribution

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1022

EP - 1025

BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016

Y2 - 22 May 2016 through 25 May 2016

ER -

Ko J, Yang Y, Jung SO, Kim J, Lee CA, Min YS et al. WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1022-1025. 7527417. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2016.7527417

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

Abstract

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