VLSI architecture of CDMA rake receiver with low hardware complexity for PCS

Seongjoo Lee; Sangyun Hwang; Jaeseok Kim

VLSI architecture of CDMA rake receiver with low hardware complexity for PCS

Seongjoo Lee, Sangyun Hwang, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30 K logic gates. We also implemented our system on FPGA chips and it was successfully tested.

Original language	English
Pages (from-to)	160-161
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication status	Published - 1998
Event	Proceedings of the 1998 17th Conference on Consumer Electronics - Los Angeles, CA, USA Duration: 1998 Jun 2 → 1998 Jun 4

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Cite this

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title = "VLSI architecture of CDMA rake receiver with low hardware complexity for PCS",

abstract = "In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30 K logic gates. We also implemented our system on FPGA chips and it was successfully tested.",

author = "Seongjoo Lee and Sangyun Hwang and Jaeseok Kim",

year = "1998",

language = "English",

pages = "160--161",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

issn = "0747-668X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 17th Conference on Consumer Electronics ; Conference date: 02-06-1998 Through 04-06-1998",

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TY - JOUR

T1 - VLSI architecture of CDMA rake receiver with low hardware complexity for PCS

AU - Lee, Seongjoo

AU - Hwang, Sangyun

AU - Kim, Jaeseok

PY - 1998

Y1 - 1998

N2 - In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30 K logic gates. We also implemented our system on FPGA chips and it was successfully tested.

AB - In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30 K logic gates. We also implemented our system on FPGA chips and it was successfully tested.

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M3 - Conference article

AN - SCOPUS:0031642766

SN - 0747-668X

SP - 160

EP - 161

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

T2 - Proceedings of the 1998 17th Conference on Consumer Electronics

Y2 - 2 June 1998 through 4 June 1998

ER -

VLSI architecture of CDMA rake receiver with low hardware complexity for PCS

Abstract

All Science Journal Classification (ASJC) codes

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