Video encoder/decoder architecture for consumer-use HD-DVCRs

Sang Jun An, Heung Chul Oh, Tae Young Lee, Yong Hwan Lee, Jae Seok Kim, Yong Surk Lee

Research output: Contribution to journalConference articlepeer-review


In this paper, we propose a video encoder/decoder architecture for HD-DVCRs based on the `Specifications of Consumer-Use Digital VCRs'. To reduce hardware complexity a novel QNO selection algorithm is developed. The arranging algorithm of a segment is implemented with minimal memory and most hardware is shared in the encoding/decoding process. The proposed architecture's target operating frequency is 54 MHz and it will be fabricated using 3-layer metal 0.6 um CMOS process technology.

Original languageEnglish
Pages (from-to)54-55
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication statusPublished - 1997
EventProceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA
Duration: 1997 Jun 111997 Jun 13

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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