V th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

S. H. Lee; J. Huang; P. Majhi; P. D. Kirsch; B. G. Min; C. S. Park; J. Oh; W. Y. Loh; C. Y. Kang; B. Sassman; P. Y. Hung; S. McCoy; J. Chen; B. Wu; G. Moori; D. Heh; C. Young; G. Bersuker; H. H. Tseng; S. K. Banerjee; R. Jammy

V _th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

S. H. Lee, J. Huang, P. Majhi, P. D. Kirsch, B. G. Min, C. S. Park, J. Oh, W. Y. Loh, C. Y. Kang, B. Sassman, P. Y. Hung, S. McCoy, J. Chen, B. Wu, G. Moori, D. Heh, C. Young, G. Bersuker, H. H. Tseng, S. K. BanerjeeR. Jammy

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Citations (Scopus)

Abstract

We have studied key parameters for controlling threshold voltage (V _th) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V _th variation same to Si unlike RTA anneal while still having 2.8x mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V _th [-0.2∼-0.3V], ∼1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.

Original language	English
Title of host publication	2009 Symposium on VLSI Technology, VLSIT 2009
Pages	74-75
Number of pages	2
Publication status	Published - 2009
Event	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Lee, S. H., Huang, J., Majhi, P., Kirsch, P. D., Min, B. G., Park, C. S., Oh, J., Loh, W. Y., Kang, C. Y., Sassman, B., Hung, P. Y., McCoy, S., Chen, J., Wu, B., Moori, G., Heh, D., Young, C., Bersuker, G., Tseng, H. H., ... Jammy, R. (2009). V _th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 74-75). [5200639] (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{6a02acd119024e31b32f733936a076f7,

title = "V th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node",

abstract = "We have studied key parameters for controlling threshold voltage (V th) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V th variation same to Si unlike RTA anneal while still having 2.8x mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V th [-0.2∼-0.3V], ∼1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.",

author = "Lee, {S. H.} and J. Huang and P. Majhi and Kirsch, {P. D.} and Min, {B. G.} and Park, {C. S.} and J. Oh and Loh, {W. Y.} and Kang, {C. Y.} and B. Sassman and Hung, {P. Y.} and S. McCoy and J. Chen and B. Wu and G. Moori and D. Heh and C. Young and G. Bersuker and Tseng, {H. H.} and Banerjee, {S. K.} and R. Jammy",

year = "2009",

language = "English",

isbn = "9784863480094",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "74--75",

booktitle = "2009 Symposium on VLSI Technology, VLSIT 2009",

note = "2009 Symposium on VLSI Technology, VLSIT 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

Lee, SH, Huang, J, Majhi, P, Kirsch, PD, Min, BG, Park, CS, Oh, J, Loh, WY, Kang, CY, Sassman, B, Hung, PY, McCoy, S, Chen, J, Wu, B, Moori, G, Heh, D, Young, C, Bersuker, G, Tseng, HH, Banerjee, SK & Jammy, R 2009, V _th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node. in 2009 Symposium on VLSI Technology, VLSIT 2009., 5200639, Digest of Technical Papers - Symposium on VLSI Technology, pp. 74-75, 2009 Symposium on VLSI Technology, VLSIT 2009, Kyoto, Japan, 09/6/16.

V _th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node. / Lee, S. H.; Huang, J.; Majhi, P. et al.
2009 Symposium on VLSI Technology, VLSIT 2009. 2009. p. 74-75 5200639 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - V th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

AU - Lee, S. H.

AU - Huang, J.

AU - Majhi, P.

AU - Kirsch, P. D.

AU - Min, B. G.

AU - Park, C. S.

AU - Oh, J.

AU - Loh, W. Y.

AU - Kang, C. Y.

AU - Sassman, B.

AU - Hung, P. Y.

AU - McCoy, S.

AU - Chen, J.

AU - Wu, B.

AU - Moori, G.

AU - Heh, D.

AU - Young, C.

AU - Bersuker, G.

AU - Tseng, H. H.

AU - Banerjee, S. K.

AU - Jammy, R.

PY - 2009

Y1 - 2009

N2 - We have studied key parameters for controlling threshold voltage (V th) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V th variation same to Si unlike RTA anneal while still having 2.8x mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V th [-0.2∼-0.3V], ∼1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.

AB - We have studied key parameters for controlling threshold voltage (V th) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V th variation same to Si unlike RTA anneal while still having 2.8x mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V th [-0.2∼-0.3V], ∼1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.

UR - http://www.scopus.com/inward/record.url?scp=71049183125&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71049183125&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:71049183125

SN - 9784863480094

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 74

EP - 75

BT - 2009 Symposium on VLSI Technology, VLSIT 2009

T2 - 2009 Symposium on VLSI Technology, VLSIT 2009

Y2 - 16 June 2009 through 18 June 2009

ER -