TY - JOUR
T1 - Unsupervised novelty pattern classification of shmoo plots for visualizing the test results of integrated circuits
AU - Shin, Hyun Soo
AU - Kim, Youngju
AU - Kim, Chang Ouk
AU - Park, Sung Ho
N1 - Publisher Copyright:
© 2022 Elsevier Ltd
PY - 2022/9/15
Y1 - 2022/9/15
N2 - Shmoo plots are visual tools for verifying the performance of integrated circuit devices, where each cell in a plot records whether the examined device operates normally under the test condition. When identifying the device state, the overall pass/fail pattern appearing in the shmoo plot is more important than the test results for individual conditions. Because similar shmoo plots indicate similar device characteristics, defect causes, and process peculiarities, engineers can analyze device quality and defect causes by classifying shmoo plot patterns. Most mass-produced devices have high and stable yields, whereas defect devices are incredibly scarce. If engineers classify numerous device plots manually at a semiconductor test site, significant time and resources will be required, and the result will likely vary based on the engineers’ experience. Therefore, shmoo plot usage is limited unless an automatic classification model is adopted. Moreover, training high-performance pattern classifiers that do not overfit the models is difficult because shmoo plots contain high-dimensional data and unlabeled, multiclass imbalanced datasets, where the number of defects is smaller than that of normal plots and pattern labels are seldom assigned. In this study, we propose a novel feature extraction process and a two-stage clustering process to distinguish novel shmoo plot patterns. Actual shmoo plots obtained from a wafer test stage are used to compare the experimental results obtained via the proposed method and conventional methods, and they verify the superiority of the proposed method.
AB - Shmoo plots are visual tools for verifying the performance of integrated circuit devices, where each cell in a plot records whether the examined device operates normally under the test condition. When identifying the device state, the overall pass/fail pattern appearing in the shmoo plot is more important than the test results for individual conditions. Because similar shmoo plots indicate similar device characteristics, defect causes, and process peculiarities, engineers can analyze device quality and defect causes by classifying shmoo plot patterns. Most mass-produced devices have high and stable yields, whereas defect devices are incredibly scarce. If engineers classify numerous device plots manually at a semiconductor test site, significant time and resources will be required, and the result will likely vary based on the engineers’ experience. Therefore, shmoo plot usage is limited unless an automatic classification model is adopted. Moreover, training high-performance pattern classifiers that do not overfit the models is difficult because shmoo plots contain high-dimensional data and unlabeled, multiclass imbalanced datasets, where the number of defects is smaller than that of normal plots and pattern labels are seldom assigned. In this study, we propose a novel feature extraction process and a two-stage clustering process to distinguish novel shmoo plot patterns. Actual shmoo plots obtained from a wafer test stage are used to compare the experimental results obtained via the proposed method and conventional methods, and they verify the superiority of the proposed method.
KW - Class imbalance
KW - Clustering
KW - Feature extraction
KW - High dimensionality
KW - Shmoo plot
KW - Unlabeled data
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U2 - 10.1016/j.eswa.2022.117341
DO - 10.1016/j.eswa.2022.117341
M3 - Article
AN - SCOPUS:85128991650
SN - 0957-4174
VL - 202
JO - Expert Systems with Applications
JF - Expert Systems with Applications
M1 - 117341
ER -