Aprocess for the self-limited layer synthesis (SLS) of WSe2 on SiO2 substrates has been developed that provides systematic layer number controllability with micrometer-scale (>90%) and wafer-scale (∼8 cm) uniformity suitable electronic and optoelectronic device applications. This was confirmed by the fabrication and testing of a WSe2 back-gated field effect transistor (FET) using Pd (30 nm) as the contact metal, which exhibited p-type behavior with an on/off ratio of∼106 and a field-effect hole mobility of 2.2 cm2 V-1 s-1 value, which was higher than has been reported for WSe2-based FETs produced by conventional chemical vapor deposition. Onthe basis of these results, it is proposed that the SLS method is universally applicable to a range of device applications.
|Publication status||Published - 2016 Jan 22|
Bibliographical noteFunding Information:
This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848); this work was supported by Korea Evaluation Institute of Industrial Technology (KEIT) funded by the Ministry of Trade, Industry and Energy (MOTIE) (Project No. 10050296, Large scale (Over 8") synthesis and evaluation technology of twodimensional chalcogenides for next generation electronic devices); this work was supported by Samsung Display Co., Ltd.; and a National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. NRF-2014R1A2A1A11052588).
© 2016 IOP Publishing Ltd.
All Science Journal Classification (ASJC) codes
- Materials Science(all)
- Condensed Matter Physics
- Mechanics of Materials
- Mechanical Engineering