Tunnelling-based ternary metal–oxide–semiconductor technology

Jae Won Jeong; Young Eun Choi; Woo Seok Kim; Jee Ho Park; Sunmean Kim; Sunhae Shin; Kyuho Lee; Jiwon Chang; Seong Jin Kim; Kyung Rok Kim

doi:10.1038/s41928-019-0272-8

Tunnelling-based ternary metal–oxide–semiconductor technology

Jae Won Jeong, Young Eun Choi, Woo Seok Kim, Jee Ho Park, Sunmean Kim, Sunhae Shin, Kyuho Lee, Jiwon Chang, Seong Jin Kim, Kyung Rok Kim

School of System & Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

67 Citations (Scopus)

Abstract

The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.

Original language	English
Pages (from-to)	307-312
Number of pages	6
Journal	Nature Electronics
Volume	2
Issue number	7
DOIs	https://doi.org/10.1038/s41928-019-0272-8
Publication status	Published - 2019 Jul 1

Bibliographical note

Funding Information:
This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes.

Publisher Copyright:
© 2019, The Author(s), under exclusive licence to Springer Nature Limited.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Instrumentation
Electrical and Electronic Engineering

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10.1038/s41928-019-0272-8

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@article{87147268b67b4b8d89e537633ba98aa0,

title = "Tunnelling-based ternary metal–oxide–semiconductor technology",

abstract = "The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.",

author = "Jeong, {Jae Won} and Choi, {Young Eun} and Kim, {Woo Seok} and Park, {Jee Ho} and Sunmean Kim and Sunhae Shin and Kyuho Lee and Jiwon Chang and Kim, {Seong Jin} and Kim, {Kyung Rok}",

note = "Funding Information: This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes. Publisher Copyright: {\textcopyright} 2019, The Author(s), under exclusive licence to Springer Nature Limited.",

year = "2019",

month = jul,

day = "1",

doi = "10.1038/s41928-019-0272-8",

language = "English",

volume = "2",

pages = "307--312",

journal = "Nature Electronics",

issn = "2520-1131",

publisher = "Nature Publishing Group",

number = "7",

}

TY - JOUR

T1 - Tunnelling-based ternary metal–oxide–semiconductor technology

AU - Jeong, Jae Won

AU - Choi, Young Eun

AU - Kim, Woo Seok

AU - Park, Jee Ho

AU - Kim, Sunmean

AU - Shin, Sunhae

AU - Lee, Kyuho

AU - Chang, Jiwon

AU - Kim, Seong Jin

AU - Kim, Kyung Rok

N1 - Funding Information: This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes. Publisher Copyright: © 2019, The Author(s), under exclusive licence to Springer Nature Limited.

PY - 2019/7/1

Y1 - 2019/7/1

N2 - The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.

AB - The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=85069442467&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85069442467&partnerID=8YFLogxK

U2 - 10.1038/s41928-019-0272-8

DO - 10.1038/s41928-019-0272-8

M3 - Article

AN - SCOPUS:85069442467

SN - 2520-1131

VL - 2

SP - 307

EP - 312

JO - Nature Electronics

JF - Nature Electronics

IS - 7

ER -

Tunnelling-based ternary metal–oxide–semiconductor technology

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