The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
Bibliographical noteFunding Information:
This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes.
© 2019, The Author(s), under exclusive licence to Springer Nature Limited.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering