Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Hanwool Jeong, Taewon Kim, Taejoong Song, Gyuhong Kim, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)


A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

Original languageEnglish
Article number6876016
Pages (from-to)1370-1374
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
Publication statusPublished - 2015 Jul 1

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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