Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Hanwool Jeong; Taewon Kim; Taejoong Song; Gyuhong Kim; Seong Ook Jung

doi:10.1109/TVLSI.2014.2337958

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Hanwool Jeong, Taewon Kim, Taejoong Song, Gyuhong Kim, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

Original language	English
Article number	6876016
Pages (from-to)	1370-1374
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	23
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2014.2337958
Publication status	Published - 2015 Jul 1

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2014.2337958

Cite this

@article{b89602ebd7e048e386d9c69423ecc8ef,

title = "Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM",

abstract = "A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.",

author = "Hanwool Jeong and Taewon Kim and Taejoong Song and Gyuhong Kim and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

year = "2015",

month = jul,

day = "1",

doi = "10.1109/TVLSI.2014.2337958",

language = "English",

volume = "23",

pages = "1370--1374",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

AU - Jeong, Hanwool

AU - Kim, Taewon

AU - Song, Taejoong

AU - Kim, Gyuhong

AU - Jung, Seong Ook

PY - 2015/7/1

Y1 - 2015/7/1

N2 - A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

AB - A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

UR - http://www.scopus.com/inward/record.url?scp=85027929108&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027929108&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2014.2337958

DO - 10.1109/TVLSI.2014.2337958

M3 - Article

AN - SCOPUS:85027929108

SN - 1063-8210

VL - 23

SP - 1370

EP - 1374

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 7

M1 - 6876016

ER -

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this