Transistor sizing for reliable domino logic design in dual threshold voltage technologies

S. O. Jung; K. W. Kim; S. M. Kang

doi:10.1145/368122.368900

Transistor sizing for reliable domino logic design in dual threshold voltage technologies

S. O. Jung, K. W. Kim, S. M. Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.

Original language	English
Pages (from-to)	133-138
Number of pages	6
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/368122.368900
Publication status	Published - 2001
Event	11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States Duration: 2001 Mar 22 → 2001 Mar 23

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1145/368122.368900

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abstract = "Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.",

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journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

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AU - Jung, S. O.

AU - Kim, K. W.

AU - Kang, S. M.

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N2 - Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.

AB - Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.

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JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

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ER -

Transistor sizing for reliable domino logic design in dual threshold voltage technologies

Abstract

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