Timing window wiper: A new scheme for reducing refresh power of DRAM

Ho Hyun Shin; Hyeokjun Seo; Byunghoon Lee; Jeongbin Kim; Eui Young Chung

doi:10.1109/ASPDAC.2017.7858309

Timing window wiper: A new scheme for reducing refresh power of DRAM

Ho Hyun Shin, Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim, Eui Young Chung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

DRAM refresh power, which is consumed solely to preserve data, is rapidly increasing as capacity increases. A study predicts that the power will account for up to 35% of total DRAM power in the high capacity DRAM device. While various schemes were proposed to reduce the refresh power, those could not be adopted to commercial products due to cost overhead and design complexity issues. In this paper, we propose a simple refresh power saving scheme called TWW. We implement it with a much smaller amount of register size than previous works without modification on OS and DRAM controller. It eliminates unnecessary refresh operation of pre-activated rows in a specific timing window with optimum register size. We can save the refresh power up to 16% with only 6.2 KB registers in a DRAM device. This paper explains the implementation of the proposed scheme and shows the power saving effectiveness with gem5 full system simulator.

Original language	English
Title of host publication	2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	133-138
Number of pages	6
ISBN (Electronic)	9781509015580
DOIs	https://doi.org/10.1109/ASPDAC.2017.7858309
Publication status	Published - 2017 Feb 16
Event	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan Duration: 2017 Jan 16 → 2017 Jan 19

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Country/Territory	Japan
City	Chiba
Period	17/1/16 → 17/1/19

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ASPDAC.2017.7858309

Cite this

Shin, H. H., Seo, H., Lee, B., Kim, J., & Chung, E. Y. (2017). Timing window wiper: A new scheme for reducing refresh power of DRAM. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 (pp. 133-138). Article 7858309 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2017.7858309

@inproceedings{2e3362f3c68a40b3a53d9d041bb9907b,

title = "Timing window wiper: A new scheme for reducing refresh power of DRAM",

abstract = "DRAM refresh power, which is consumed solely to preserve data, is rapidly increasing as capacity increases. A study predicts that the power will account for up to 35% of total DRAM power in the high capacity DRAM device. While various schemes were proposed to reduce the refresh power, those could not be adopted to commercial products due to cost overhead and design complexity issues. In this paper, we propose a simple refresh power saving scheme called TWW. We implement it with a much smaller amount of register size than previous works without modification on OS and DRAM controller. It eliminates unnecessary refresh operation of pre-activated rows in a specific timing window with optimum register size. We can save the refresh power up to 16% with only 6.2 KB registers in a DRAM device. This paper explains the implementation of the proposed scheme and shows the power saving effectiveness with gem5 full system simulator.",

author = "Shin, {Ho Hyun} and Hyeokjun Seo and Byunghoon Lee and Jeongbin Kim and Chung, {Eui Young}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 ; Conference date: 16-01-2017 Through 19-01-2017",

year = "2017",

month = feb,

day = "16",

doi = "10.1109/ASPDAC.2017.7858309",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "133--138",

booktitle = "2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017",

address = "United States",

}

Shin, HH, Seo, H, Lee, B, Kim, J & Chung, EY 2017, Timing window wiper: A new scheme for reducing refresh power of DRAM. in 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017., 7858309, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 133-138, 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, 17/1/16. https://doi.org/10.1109/ASPDAC.2017.7858309

Timing window wiper: A new scheme for reducing refresh power of DRAM. / Shin, Ho Hyun; Seo, Hyeokjun; Lee, Byunghoon et al.
2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 133-138 7858309 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Timing window wiper

T2 - 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017

AU - Shin, Ho Hyun

AU - Seo, Hyeokjun

AU - Lee, Byunghoon

AU - Kim, Jeongbin

AU - Chung, Eui Young

PY - 2017/2/16

Y1 - 2017/2/16

N2 - DRAM refresh power, which is consumed solely to preserve data, is rapidly increasing as capacity increases. A study predicts that the power will account for up to 35% of total DRAM power in the high capacity DRAM device. While various schemes were proposed to reduce the refresh power, those could not be adopted to commercial products due to cost overhead and design complexity issues. In this paper, we propose a simple refresh power saving scheme called TWW. We implement it with a much smaller amount of register size than previous works without modification on OS and DRAM controller. It eliminates unnecessary refresh operation of pre-activated rows in a specific timing window with optimum register size. We can save the refresh power up to 16% with only 6.2 KB registers in a DRAM device. This paper explains the implementation of the proposed scheme and shows the power saving effectiveness with gem5 full system simulator.

AB - DRAM refresh power, which is consumed solely to preserve data, is rapidly increasing as capacity increases. A study predicts that the power will account for up to 35% of total DRAM power in the high capacity DRAM device. While various schemes were proposed to reduce the refresh power, those could not be adopted to commercial products due to cost overhead and design complexity issues. In this paper, we propose a simple refresh power saving scheme called TWW. We implement it with a much smaller amount of register size than previous works without modification on OS and DRAM controller. It eliminates unnecessary refresh operation of pre-activated rows in a specific timing window with optimum register size. We can save the refresh power up to 16% with only 6.2 KB registers in a DRAM device. This paper explains the implementation of the proposed scheme and shows the power saving effectiveness with gem5 full system simulator.

UR - http://www.scopus.com/inward/record.url?scp=85015334601&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85015334601&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2017.7858309

DO - 10.1109/ASPDAC.2017.7858309

M3 - Conference contribution

AN - SCOPUS:85015334601

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 133

EP - 138

BT - 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 16 January 2017 through 19 January 2017

ER -

Shin HH, Seo H, Lee B, Kim J, Chung EY. Timing window wiper: A new scheme for reducing refresh power of DRAM. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 133-138. 7858309. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2017.7858309

Timing window wiper: A new scheme for reducing refresh power of DRAM

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