Timing verification with the non-periodic gated clocking

Hanbin Kim, Eui Young Chung, Kyu Myung Choi, Jeong Taek Kong, Sang Hoon Lee

Research output: Contribution to journalConference articlepeer-review


Digital circuits can be implemented based on highly complex non-periodic clocking schemes. However, the conventional timing verifiers do not guarantee the correctness of timing analysis because they cannot consider full timing behaviors of a gated clock. This paper describes a novel hybrid timing verification approach which handles circuits using non-periodic gated clocking schemes. For its non-periodic nature of the gated clock, timing constraints must be generated with considering full behaviors of the gated clock. Experimental results show that the proposed technique performs more complete and more reliable timing verification than conventional timing verifiers.

Original languageEnglish
Pages (from-to)528-531
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1996
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
Duration: 1996 May 121996 May 15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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