Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors

Suehye Park, Edward Namkyu Cho, Ilgu Yun

Research output: Contribution to journalArticlepeer-review

22 Citations (Scopus)


The demand for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) has increased due to the high mobility and suitability for low temperature fabrication. A prediction of the threshold voltage shift (ΔV th) under bias stress is required for the commercial use of a-IGZO TFTs. We have investigated effects of the channel length and alternating pulse bias (positive and negative gate bias stress in sequence) with different positive gate bias values (V GS+) on ΔV th. We found that ΔV th increases as the channel length decreases or V GS+ increases, due to the increase in the charge trapping rate. Finally, the degradation behaviors of a-IGZO TFTs are predicted.

Original languageEnglish
Pages (from-to)2215-2219
Number of pages5
JournalMicroelectronics Reliability
Issue number9-10
Publication statusPublished - 2012 Sept

Bibliographical note

Funding Information:
This work was supported by Yonsei University, Institute of TMS Information Technology, a Brain Korea 21 program, Korea.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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