The performance of message passing architecture machines is often ameliorated by devising alternative message passing strategies. A number have been proposed for incorporation into the design of architectures for massively parallel machines. Among these approaches are (i) static machine topologies supporting packet switched message routing (store-and-forward) (ii) dynamic machine topologies supporting circuit switched routing and (iii) shared memory systems. This paper reports the results of analytical modelling of these strategies - verifying the results by experimentation on a large reconfigurable transputer machine (the ParSiFal T-Rack). A family of hybrid architectures called the Hyper-Dynamic Architecture is then proposed which incorporates both packet switched and circuit switched features. Extrapolation of the verified analytical models and various simulation results obtained under realistic environments then allow some prediction of the potential performance of such architectures.
|Title of host publication||ICS 1991 - Proceedings of the 5th International Conference on Supercomputing|
|Editors||Edward S. Davidson, Friedel Hossfield|
|Publisher||Association for Computing Machinery|
|Number of pages||11|
|ISBN (Print)||0897914341, 9780897914345|
|Publication status||Published - 1991 Jun 1|
|Event||5th International Conference on Supercomputing, ICS 1991 - Cologne, Germany|
Duration: 1991 Jun 17 → 1991 Jun 21
|Name||Proceedings of the International Conference on Supercomputing|
|Conference||5th International Conference on Supercomputing, ICS 1991|
|Period||91/6/17 → 91/6/21|
Bibliographical noteFunding Information:
The T-Rack is a flexible and extensible MIMD system, which has been designed and fabricated at the University of Manchester as part of the UK Alvey funded ParSiFal project (Alvey/SERC grant number GR/D/59281-IKBS/146). single T-Rack is hosted by a SUN3/160 colour workstation and incorporates 64 processing elements, each processing element comprising an INMOS T800 transputer  together with o]ne or two megabytes of external RAM. A further processing element comprising a T~14 transputer and 2 megabytes c,f external RAM is utilised as part of the host subeystem. Yet another processing element comprising a T800 transputer and up to 8 Megabytes of external RAM is intended for use as part of a control subsystem. wide
out as part of the UK Alvey projects (Alvey/SERC grant 146 and SERC grant number Hojung Cha wishes to express of South Korea for financial to express their thanks to their the University of Manchester.
© 1991 ACM.
All Science Journal Classification (ASJC) codes
- Computer Science(all)