The Formation of Ti-Polycide Gate Structure with High Thermal Stability Using Chemical-Mechanical Polishing (CMP) Planarization Technology

Hyoung Sub Kim; Dae Hong Ko; Dae Lok Bae; Kazuyuki Fujihara; Ho Kyu Kang

doi:10.1109/55.740660

The Formation of Ti-Polycide Gate Structure with High Thermal Stability Using Chemical-Mechanical Polishing (CMP) Planarization Technology

Hyoung Sub Kim, Dae Hong Ko, Dae Lok Bae, Kazuyuki Fujihara, Ho Kyu Kang

Department of Materials Science and Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi₂ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region.

Original language	English
Pages (from-to)	86-88
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	20
Issue number	2
DOIs	https://doi.org/10.1109/55.740660
Publication status	Published - 1999 Feb

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/55.740660

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abstract = "A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi2 gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region.",

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AU - Fujihara, Kazuyuki

AU - Kang, Ho Kyu

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AB - A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi2 gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region.

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The Formation of Ti-Polycide Gate Structure with High Thermal Stability Using Chemical-Mechanical Polishing (CMP) Planarization Technology

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