Abstract
Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.
Original language | English |
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Title of host publication | Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 219-222 |
Number of pages | 4 |
ISBN (Electronic) | 0780364708, 9780780364707 |
DOIs | |
Publication status | Published - 2000 |
Event | 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 - Cheju, Korea, Republic of Duration: 2000 Aug 28 → 2000 Aug 30 |
Publication series
Name | Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 |
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Other
Other | 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 |
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Country/Territory | Korea, Republic of |
City | Cheju |
Period | 00/8/28 → 00/8/30 |
Bibliographical note
Publisher Copyright:© 2000 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering