TY - GEN
T1 - Test scheduling using Ant Colony Optimization for 3D integrated circuits
AU - Choi, Inhyuk
AU - Han, Taewoo
AU - Kang, Sungho
PY - 2013
Y1 - 2013
N2 - Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.
AB - Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.
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U2 - 10.1109/ISOCC.2013.6863973
DO - 10.1109/ISOCC.2013.6863973
M3 - Conference contribution
AN - SCOPUS:84906912232
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 15
EP - 16
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -