Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Young Woo Lee; Inhyuk Choi; Kang Hoon Oh; James Jinsoo Ko; Sungho Kang

doi:10.1109/ITC-ASIA.2017.8097131

Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Young Woo Lee, Inhyuk Choi, Kang Hoon Oh, James Jinsoo Ko, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

Original language	English
Title of host publication	ITC-Asia 2017 - International Test Conference in Asia
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	150-154
Number of pages	5
ISBN (Electronic)	9781538630518
DOIs	https://doi.org/10.1109/ITC-ASIA.2017.8097131
Publication status	Published - 2017 Nov 3
Event	1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan, Province of China Duration: 2017 Sept 13 → 2017 Sept 15

Publication series

Name	ITC-Asia 2017 - International Test Conference in Asia

Conference

Conference	1st International Test Conference in Asia, ITC-Asia 2017
Country/Territory	Taiwan, Province of China
City	Taipei
Period	17/9/13 → 17/9/15

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MISP) (No. 2015R1A2A1A13001751).

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Automotive Engineering
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ITC-ASIA.2017.8097131

Cite this

Lee, Y. W., Choi, I., Oh, K. H., Ko, J. J., & Kang, S. (2017). Test item priority estimation for high parallel test efficiency under ATE debug time constraints. In ITC-Asia 2017 - International Test Conference in Asia (pp. 150-154). [8097131] (ITC-Asia 2017 - International Test Conference in Asia). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-ASIA.2017.8097131

@inproceedings{d3d6af1254894f27a8b0db6041368d2b,

title = "Test item priority estimation for high parallel test efficiency under ATE debug time constraints",

abstract = "Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.",

author = "Lee, {Young Woo} and Inhyuk Choi and Oh, {Kang Hoon} and Ko, {James Jinsoo} and Sungho Kang",

note = "Funding Information: This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MISP) (No. 2015R1A2A1A13001751). Publisher Copyright: {\textcopyright} 2017 IEEE.; 1st International Test Conference in Asia, ITC-Asia 2017 ; Conference date: 13-09-2017 Through 15-09-2017",

year = "2017",

month = nov,

day = "3",

doi = "10.1109/ITC-ASIA.2017.8097131",

language = "English",

series = "ITC-Asia 2017 - International Test Conference in Asia",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "150--154",

booktitle = "ITC-Asia 2017 - International Test Conference in Asia",

address = "United States",

}

Lee, YW, Choi, I, Oh, KH, Ko, JJ & Kang, S 2017, Test item priority estimation for high parallel test efficiency under ATE debug time constraints. in ITC-Asia 2017 - International Test Conference in Asia., 8097131, ITC-Asia 2017 - International Test Conference in Asia, Institute of Electrical and Electronics Engineers Inc., pp. 150-154, 1st International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, Province of China, 17/9/13. https://doi.org/10.1109/ITC-ASIA.2017.8097131

Test item priority estimation for high parallel test efficiency under ATE debug time constraints. / Lee, Young Woo; Choi, Inhyuk; Oh, Kang Hoon et al.
ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., 2017. p. 150-154 8097131 (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Test item priority estimation for high parallel test efficiency under ATE debug time constraints

AU - Lee, Young Woo

AU - Choi, Inhyuk

AU - Oh, Kang Hoon

AU - Ko, James Jinsoo

AU - Kang, Sungho

N1 - Funding Information: This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MISP) (No. 2015R1A2A1A13001751). Publisher Copyright: © 2017 IEEE.

PY - 2017/11/3

Y1 - 2017/11/3

N2 - Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

AB - Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

UR - http://www.scopus.com/inward/record.url?scp=85040615236&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85040615236&partnerID=8YFLogxK

U2 - 10.1109/ITC-ASIA.2017.8097131

DO - 10.1109/ITC-ASIA.2017.8097131

M3 - Conference contribution

AN - SCOPUS:85040615236

T3 - ITC-Asia 2017 - International Test Conference in Asia

SP - 150

EP - 154

BT - ITC-Asia 2017 - International Test Conference in Asia

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st International Test Conference in Asia, ITC-Asia 2017

Y2 - 13 September 2017 through 15 September 2017

ER -

Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this