Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.
|Title of host publication||ITC-Asia 2017 - International Test Conference in Asia|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|Publication status||Published - 2017 Nov 3|
|Event||1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan, Province of China|
Duration: 2017 Sept 13 → 2017 Sept 15
|Name||ITC-Asia 2017 - International Test Conference in Asia|
|Conference||1st International Test Conference in Asia, ITC-Asia 2017|
|Country/Territory||Taiwan, Province of China|
|Period||17/9/13 → 17/9/15|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MISP) (No. 2015R1A2A1A13001751).
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Automotive Engineering
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality