Test-Friendly Data-Selectable Self-Gating (DSSG)

Jihye Kim, Sangjun Lee, Sungho Kang

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


Low-power design is a key consideration in modern design. XOR self-gating (data-driven self-gating) is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. When applying XOR self-gating, dynamic power consumption is reduced, but the number of required test patterns on the testing side is inflated. In critical cases, more than three times the regular number of scan test patterns may be required for industrial designs, such as GPUs. In this brief, we propose a novel self-gating structure. Data-selectable self-gating (DSSG) is designed to use functional data and scan data selectively to eliminate the unnecessary clock toggling of flip-flops. With this structure, the self-gating function can be used in the scan test mode, as well as the function mode. When the self-gating logic is used during scan shift operations, the stuck-at faults in the self-gating logic can be tested with short test sequences; therefore, the rise in test costs can be mitigated. It is possible to test the stuck-at faults in self-gating logic using only four scan test patterns. The experimental results show that the average of the stuck-at test pattern increase ratio has been dropped from more than 90% to less than 8%. The low-power performance of the proposed method in the mission mode is the same as that of the conventional self-gating structures. When the DSSG method is used, the dynamic power of the shift operation which may increase excessively during the scan test can be reduced.

Original languageEnglish
Article number8728193
Pages (from-to)1972-1976
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number8
Publication statusPublished - 2019 Aug

Bibliographical note

Funding Information:
Manuscript received December 19, 2018; revised March 18, 2019 and April 16, 2019; accepted May 3, 2019. Date of publication June 3, 2019; date of current version July 24, 2019. This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology devel-

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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