Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

Inhyuk Choi; Hyunggoy Oh; Sungho Kang

doi:10.1109/APCCAS.2016.7804019

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

Inhyuk Choi, Hyunggoy Oh, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	522-525
Number of pages	4
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7804019
Publication status	Published - 2017 Jan 3
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 25 → 2016 Oct 28

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/25 → 16/10/28

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MISP) (No. 2015R1A2A1A13001751)

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Signal Processing

Access to Document

10.1109/APCCAS.2016.7804019

Cite this

Choi, I., Oh, H., & Kang, S. (2017). Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 522-525). Article 7804019 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804019

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Choi, I, Oh, H & Kang, S 2017, Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7804019, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 522-525, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7804019

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. / Choi, Inhyuk; Oh, Hyunggoy; Kang, Sungho.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 522-525 7804019 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Choi I, Oh H, Kang S. Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 522-525. 7804019. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). doi: 10.1109/APCCAS.2016.7804019

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

Abstract

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