Systematic studies on low-voltage pentacene thin-film transistors with low- k polymer/high- k Oxide bilayer gate dielectric

We report on the fabrication and characterization of pentacene based thin-film transistors (TFTs) with low- k poly-4-vinylphenol (PVP)/high- k yttrium oxide (YOx) bilayer gate dielectrics of various thickness combinations, for the thin-PVP layers (45, 70, and 140 nm) and for the thin YOx (50 and 100 nm). Neither YOx nor thin-PVP single layer film alone can properly function as a dielectric layer due to their very high leakage current. However, our bilayer films of six different thickness combinations (among which the thinnest was PVP YOx =4550 nm while the thickest was PVP YOx =140100 nm) all exhibited quite a good dielectric strength of ∼2 MVcm, based on our maximum leakage current standard of 10-6 A cm2. All pentacene TFTs with the PVP YOx bilayer gate dielectric films successfully demonstrated good TFT characteristics at an operating voltage less than -5 V. In particular, two of our devices studied here with the bilayer combinations (45 nm thin PVP on 50 nm and 100 nm thick YOx) exhibited good device performance with field effect mobilities (1.74 and 1.05 cm2 V s) and an on/off current ratio of ∼ 104. We also demonstrate a resistance-load inverter operating below -5 V with a load resistance (RL) of 22 M connected to our pentacene TFT with a PVP (45 nm) YOx (100 nm) layer.