Surface-modified high-k oxide gate dielectrics for low-voltage high-performance pentacene thin-film transistors

Chang Su Kim, Sung Jin Jo, Sung Won Lee, Woo Jin Kim, Hong Koo Baik, Se Jong Lee

Research output: Contribution to journalArticlepeer-review

59 Citations (Scopus)


In this study, pentacene thin-film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO2-SiO2 gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis-free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4-vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, -OH groups on CeO2-SiO2 are terminated by C6H5, resulting in the formation of a more hydrophobia surface. Enhanced pentacene quality and reduced hysteresis is observed in current-voltage (I-V) measurements of the PVP-coated pentacene TFTs. Since grain boundaries and -OH groups are believed to act as electron traps, an OH-free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.

Original languageEnglish
Pages (from-to)958-962
Number of pages5
JournalAdvanced Functional Materials
Issue number6
Publication statusPublished - 2007 Apr 16

All Science Journal Classification (ASJC) codes

  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics


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