STT-MRAM sensing circuit with self-body biasing in deep submicron technologies

Conventional spin transfer torque MRAM sensing circuits suffer from a small sensing margin and a large sensing margin variation in deep submicron technologies. The small sensing margin issue becomes worse in the low-leakage process technology due to the higher threshold voltage. In this brief, the self-body biasing (self-BB) scheme is proposed to resolve the small sensing margin issue. In the self-BB scheme, the threshold voltage of load pMOS is adaptively controlled by body bias. Although leakage current flows through the body due to the positive junction bias voltage, it is well suppressed to less than 1% (0.3 μ A) of the sensing current and flows only during the sensing operation. To reduce large sensing margin variation, the source degeneration scheme with the longer channel length is used for the load pMOS. The HSPICE simulation results obtained using low-leakage 45-nm model parameters show that the proposed sensing circuit achieves a probability of the read access pass yield (^PRAPY-Memory) of 100%, whereas the sensing circuit without BB scheme has an ^P RAPY-Memory of 5.8% for a 32-Mb memory with a sensing time of 2 ns.