TY - JOUR
T1 - STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment
AU - Kim, Jeongbin
AU - Song, Yongwoon
AU - Cho, Kyungseon
AU - Lee, Hyukjun
AU - Yoon, Hongil
AU - Chung, Eui Young
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2022/5/1
Y1 - 2022/5/1
N2 - The demand for high-performance computing and rapidly increasing power consumption has increased the necessity for application-specific accelerators. In the datacenter and mobile system, more applications are increasingly relying on accelerators. Field-programmable gate arrays (FPGAs) emerge as a good candidate because they have high programmability and power efficiency. As the number of applications requiring acceleration increases, there is huge demand for FPGAs that support multiple contexts. Previous FPGA designs that support multicontext have various shortcomings such as volatility, poor power efficiency, large performance, area, and reconfiguration overhead. In this article, we propose a spin-transfer torque magnetic RAM (STT-MRAM)-based nonvolatile multicontext FPGA (NVMC-FPGA) that overcomes these shortcomings. We introduce the NVMC-FPGA architecture and operation modes that take advantage of nonvolatility and support multicontext. We also develop the multicontext-aware FPGA computer aided design flow to make the most of the NVMC-FPGA. Compared to the conventional SRAM-based FPGA, when eight identical circuits are mapped, the NVMC-FPGA improves the performance by 15.3% on average and reduces the power consumption by 11.2%-80.7%, depending on the number of simultaneously activated circuits. Moreover, when eight different circuits are mapped, the NVMC-FPGA improves the performance by 58.5% on average and reduces the power consumption by 6.2%-63.3%, depending on the number of simultaneously activated circuits.
AB - The demand for high-performance computing and rapidly increasing power consumption has increased the necessity for application-specific accelerators. In the datacenter and mobile system, more applications are increasingly relying on accelerators. Field-programmable gate arrays (FPGAs) emerge as a good candidate because they have high programmability and power efficiency. As the number of applications requiring acceleration increases, there is huge demand for FPGAs that support multiple contexts. Previous FPGA designs that support multicontext have various shortcomings such as volatility, poor power efficiency, large performance, area, and reconfiguration overhead. In this article, we propose a spin-transfer torque magnetic RAM (STT-MRAM)-based nonvolatile multicontext FPGA (NVMC-FPGA) that overcomes these shortcomings. We introduce the NVMC-FPGA architecture and operation modes that take advantage of nonvolatility and support multicontext. We also develop the multicontext-aware FPGA computer aided design flow to make the most of the NVMC-FPGA. Compared to the conventional SRAM-based FPGA, when eight identical circuits are mapped, the NVMC-FPGA improves the performance by 15.3% on average and reduces the power consumption by 11.2%-80.7%, depending on the number of simultaneously activated circuits. Moreover, when eight different circuits are mapped, the NVMC-FPGA improves the performance by 58.5% on average and reduces the power consumption by 6.2%-63.3%, depending on the number of simultaneously activated circuits.
KW - Accelerator architectures
KW - design automation
KW - field-programmable gate arrays (FPGAs)
KW - multithreading
KW - nonvolatile memory
KW - reconfigurable architectures
KW - spin-transfer torque magnetic RAM (STT-MRAM)
UR - http://www.scopus.com/inward/record.url?scp=85112425191&partnerID=8YFLogxK
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U2 - 10.1109/TCAD.2021.3091440
DO - 10.1109/TCAD.2021.3091440
M3 - Article
AN - SCOPUS:85112425191
SN - 0278-0070
VL - 41
SP - 1330
EP - 1343
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
ER -