SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Keonhee Cho; Heekyung Choi; In Jun Jung; Jisang Oh; Tae Woo Oh; Kiryong Kim; Giseok Kim; Taemin Choi; Changsoo Sim; Taejoong Song; Seong Ook Jung

doi:10.23919/VLSICircuits52068.2021.9492505

SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Keonhee Cho, Heekyung Choi, In Jun Jung, Jisang Oh, Tae Woo Oh, Kiryong Kim, Giseok Kim, Taemin Choi, Changsoo Sim, Taejoong Song, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents SRAM write-and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.

Original language	English
Title of host publication	2021 Symposium on VLSI Circuits, VLSI Circuits 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487796
DOIs	https://doi.org/10.23919/VLSICircuits52068.2021.9492505
Publication status	Published - 2021 Jun 13
Event	35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online Duration: 2021 Jun 13 → 2021 Jun 19

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2021-June

Conference

Conference	35th Symposium on VLSI Circuits, VLSI Circuits 2021
City	Virutal, Online
Period	21/6/13 → 21/6/19

Bibliographical note

Publisher Copyright:
© 2021 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSICircuits52068.2021.9492505

Cite this

Cho, K., Choi, H., Jung, I. J., Oh, J., Oh, T. W., Kim, K., Kim, G., Choi, T., Sim, C., Song, T., & Jung, S. O. (2021). SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021 Article 9492505 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSICircuits52068.2021.9492505

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title = "SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling",

abstract = "This paper presents SRAM write-and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.",

author = "Keonhee Cho and Heekyung Choi and Jung, {In Jun} and Jisang Oh and Oh, {Tae Woo} and Kiryong Kim and Giseok Kim and Taemin Choi and Changsoo Sim and Taejoong Song and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2021 JSAP.; 35th Symposium on VLSI Circuits, VLSI Circuits 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

year = "2021",

month = jun,

day = "13",

doi = "10.23919/VLSICircuits52068.2021.9492505",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 Symposium on VLSI Circuits, VLSI Circuits 2021",

address = "United States",

}

Cho, K, Choi, H, Jung, IJ, Oh, J, Oh, TW, Kim, K, Kim, G, Choi, T, Sim, C, Song, T & Jung, SO 2021, SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. in 2021 Symposium on VLSI Circuits, VLSI Circuits 2021., 9492505, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Virutal, Online, 21/6/13. https://doi.org/10.23919/VLSICircuits52068.2021.9492505

SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. / Cho, Keonhee; Choi, Heekyung; Jung, In Jun et al.
2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9492505 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

AU - Cho, Keonhee

AU - Choi, Heekyung

AU - Jung, In Jun

AU - Oh, Jisang

AU - Oh, Tae Woo

AU - Kim, Kiryong

AU - Kim, Giseok

AU - Choi, Taemin

AU - Sim, Changsoo

AU - Song, Taejoong

AU - Jung, Seong Ook

PY - 2021/6/13

Y1 - 2021/6/13

N2 - This paper presents SRAM write-and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.

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M3 - Conference contribution

AN - SCOPUS:85111860772

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2021 Symposium on VLSI Circuits, VLSI Circuits 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 35th Symposium on VLSI Circuits, VLSI Circuits 2021

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ER -

Cho K, Choi H, Jung IJ, Oh J, Oh TW, Kim K et al. SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9492505. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSICircuits52068.2021.9492505

SRAM Write-and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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