SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.