SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation

Tae Woo Oh; Seong Ook Jung

doi:10.1109/ISCAS.2018.8351146

SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation

Tae Woo Oh, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351146
Publication status	Published - 2018 Apr 26
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 2018 May 27 → 2018 May 30

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Other

Other	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	18/5/27 → 18/5/30

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2018.8351146

Cite this

Oh, T. W., & Jung, S. O. (2018). SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351146 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351146

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title = "SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation",

abstract = "This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.",

keywords = "FinFET, SRAM, data-aware write-assist, near-threshold operation, power-gating",

author = "Oh, {Tae Woo} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

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Oh, TW & Jung, SO 2018, SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351146, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 18/5/27. https://doi.org/10.1109/ISCAS.2018.8351146

SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. / Oh, Tae Woo; Jung, Seong Ook.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351146 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.

AB - This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.

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KW - data-aware write-assist

KW - near-threshold operation

KW - power-gating

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SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation

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