Software-based embedded core test using multi-polynomial for test data reduction

Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things


Other13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation


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