Abstract
Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.
Original language | English |
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Title of host publication | ISOCC 2016 - International SoC Design Conference |
Subtitle of host publication | Smart SoC for Intelligent Things |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 39-40 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
Publication status | Published - 2016 Dec 27 |
Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Publication series
Name | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
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Other
Other | 13th International SoC Design Conference, ISOCC 2016 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 16/10/23 → 16/10/26 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation