This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.
|Number of pages
|Proceedings of the Annual IEEE International ASIC Conference and Exhibit
|Published - 1995
|Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: 1995 Sept 18 → 1995 Sept 22
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering