Simulator for path-delay faults on mixed-level circuits

Y. T. Yim, Y. S. Kang, S. Kang

Research output: Contribution to journalArticlepeer-review


Most of the available path-delay fault simulators for scan environments rely on the use of augmented scan flip-flops and exclusively consider circuits composed of only discrete gates This paper describes an efficient path-delay fault simulator which operates in standard scan environments The new simulator based on a parallel pattern fault simulation algorithm can handle the switching devices by using new logic values To achieve high-speed performance, two different sets of logic values are used for the element evaluation according to the device level The results show the efficiency of the simulator.

Original languageEnglish
Pages (from-to)236-242
Number of pages7
JournalIEE Proceedings: Circuits, Devices and Systems
Issue number4
Publication statusPublished - 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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