Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

Suk Min Kim; Tae Woo Oh; Seong Ook Jung

doi:10.23919/ELINFOCOM.2018.8330545

Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

Suk Min Kim, Tae Woo Oh, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

As the DRAM process technology scales down, the offset voltage caused by the V_TH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.

Original language	English
Title of host publication	International Conference on Electronics, Information and Communication, ICEIC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538647547
DOIs	https://doi.org/10.23919/ELINFOCOM.2018.8330545
Publication status	Published - 2018 Apr 2
Event	17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States Duration: 2018 Jan 24 → 2018 Jan 27

Publication series

Name	International Conference on Electronics, Information and Communication, ICEIC 2018
Volume	2018-January

Other

Other	17th International Conference on Electronics, Information and Communication, ICEIC 2018
Country/Territory	United States
City	Honolulu
Period	18/1/24 → 18/1/27

Bibliographical note

Publisher Copyright:
© 2018 Institute of Electronics and Information Engineers.

All Science Journal Classification (ASJC) codes

Information Systems
Computer Networks and Communications
Computer Science Applications
Signal Processing
Electrical and Electronic Engineering

Access to Document

10.23919/ELINFOCOM.2018.8330545

Cite this

Kim, S. M., Oh, T. W., & Jung, S. O. (2018). Sensing voltage compensation circuit for low-power dram bit-line sense amplifier. In International Conference on Electronics, Information and Communication, ICEIC 2018 (pp. 1-4). (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2018.8330545

Kim, Suk Min ; Oh, Tae Woo ; Jung, Seong Ook. / Sensing voltage compensation circuit for low-power dram bit-line sense amplifier. International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4 (International Conference on Electronics, Information and Communication, ICEIC 2018).

@inproceedings{9da28f24424744c786832b21d42caded,

title = "Sensing voltage compensation circuit for low-power dram bit-line sense amplifier",

abstract = "As the DRAM process technology scales down, the offset voltage caused by the VTH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.",

keywords = "DRAM Bit-Line Sense Amplifier, Sensing Voltage Compensation (SVC), offset cancellation, offset voltage, sensing noise",

author = "Kim, {Suk Min} and Oh, {Tae Woo} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2018 Institute of Electronics and Information Engineers.; 17th International Conference on Electronics, Information and Communication, ICEIC 2018 ; Conference date: 24-01-2018 Through 27-01-2018",

year = "2018",

month = apr,

day = "2",

doi = "10.23919/ELINFOCOM.2018.8330545",

language = "English",

series = "International Conference on Electronics, Information and Communication, ICEIC 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "International Conference on Electronics, Information and Communication, ICEIC 2018",

address = "United States",

}

Kim, SM, Oh, TW & Jung, SO 2018, Sensing voltage compensation circuit for low-power dram bit-line sense amplifier. in International Conference on Electronics, Information and Communication, ICEIC 2018. International Conference on Electronics, Information and Communication, ICEIC 2018, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 17th International Conference on Electronics, Information and Communication, ICEIC 2018, Honolulu, United States, 18/1/24. https://doi.org/10.23919/ELINFOCOM.2018.8330545

Sensing voltage compensation circuit for low-power dram bit-line sense amplifier. / Kim, Suk Min; Oh, Tae Woo; Jung, Seong Ook.
International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

AU - Kim, Suk Min

AU - Oh, Tae Woo

AU - Jung, Seong Ook

PY - 2018/4/2

Y1 - 2018/4/2

N2 - As the DRAM process technology scales down, the offset voltage caused by the VTH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.

AB - As the DRAM process technology scales down, the offset voltage caused by the VTH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.

KW - DRAM Bit-Line Sense Amplifier

KW - Sensing Voltage Compensation (SVC)

KW - offset cancellation

KW - offset voltage

KW - sensing noise

UR - http://www.scopus.com/inward/record.url?scp=85048475244&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048475244&partnerID=8YFLogxK

U2 - 10.23919/ELINFOCOM.2018.8330545

DO - 10.23919/ELINFOCOM.2018.8330545

M3 - Conference contribution

AN - SCOPUS:85048475244

T3 - International Conference on Electronics, Information and Communication, ICEIC 2018

SP - 1

EP - 4

BT - International Conference on Electronics, Information and Communication, ICEIC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International Conference on Electronics, Information and Communication, ICEIC 2018

Y2 - 24 January 2018 through 27 January 2018

ER -

Kim SM, Oh TW, Jung SO. Sensing voltage compensation circuit for low-power dram bit-line sense amplifier. In International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (International Conference on Electronics, Information and Communication, ICEIC 2018). doi: 10.23919/ELINFOCOM.2018.8330545

Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

Abstract

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