Sensing margin trend with technology scaling in MRAM

Magnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation.