Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

Original languageEnglish
Article number8691523
Pages (from-to)2304-2315
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number8
Publication statusPublished - 2019 Aug

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time'. Together they form a unique fingerprint.

Cite this