Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

Hanwool Jeong; Juhyun Park; Seung Chul Song; Seong Ook Jung

doi:10.1109/JSSC.2019.2907774

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

19 Citations (Scopus)

Abstract

A self-timed pulsed latch (STPL) is proposed for low V_DD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

Original language	English
Article number	8691523
Pages (from-to)	2304-2315
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	8
DOIs	https://doi.org/10.1109/JSSC.2019.2907774
Publication status	Published - 2019 Aug

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2019.2907774

Cite this

@article{890241e95a4a4c47b0046cd9c7a3aea5,

title = "Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time",

abstract = "A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.",

keywords = "Flip-flop, low power, low voltage, pulsed latch, variation-aware",

author = "Hanwool Jeong and Juhyun Park and Song, {Seung Chul} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.",

year = "2019",

month = aug,

doi = "10.1109/JSSC.2019.2907774",

language = "English",

volume = "54",

pages = "2304--2315",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

AU - Jeong, Hanwool

AU - Park, Juhyun

AU - Song, Seung Chul

AU - Jung, Seong Ook

PY - 2019/8

Y1 - 2019/8

N2 - A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

AB - A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

KW - Flip-flop

KW - low power

KW - low voltage

KW - pulsed latch

KW - variation-aware

UR - http://www.scopus.com/inward/record.url?scp=85069883863&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85069883863&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2019.2907774

DO - 10.1109/JSSC.2019.2907774

M3 - Article

AN - SCOPUS:85069883863

SN - 0018-9200

VL - 54

SP - 2304

EP - 2315

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 8

M1 - 8691523

ER -

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

Abstract

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