TY - JOUR
T1 - Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction
AU - Choi, Sara
AU - Ahn, Hong Keun
AU - Song, Byungkyu
AU - Kang, Seung H.
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2021/6
Y1 - 2021/6
N2 - Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.
AB - Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.
KW - Magnetic tunnel junction (MTJ)
KW - single-ended sensing circuit
KW - spin-transfer-torque random access memory (STT-RAM)
KW - write energy
KW - write termination
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U2 - 10.1109/TCSI.2021.3069710
DO - 10.1109/TCSI.2021.3069710
M3 - Article
AN - SCOPUS:85103890474
SN - 1549-8328
VL - 68
SP - 2481
EP - 2493
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 6
M1 - 9397875
ER -