TY - GEN
T1 - Segmented scan architecture using segment for test cost reduction
AU - Yang, Myung Hoon
AU - Kim, Taejin
AU - Kim, Yongjoon
AU - Kang, Sungho
PY - 2008
Y1 - 2008
N2 - This paper presents a segmented scan architecture to both test application time and test power consumption. proposed scan architecture partitions scan chains into segments and groups these segments into several segment groups. All segments within each compatible group are filled with test vector data in parallel. Since shift operations are limited to segments, the test application and test power can be significantly reduced.
AB - This paper presents a segmented scan architecture to both test application time and test power consumption. proposed scan architecture partitions scan chains into segments and groups these segments into several segment groups. All segments within each compatible group are filled with test vector data in parallel. Since shift operations are limited to segments, the test application and test power can be significantly reduced.
UR - http://www.scopus.com/inward/record.url?scp=69949098215&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=69949098215&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2008.4815651
DO - 10.1109/SOCDC.2008.4815651
M3 - Conference contribution
AN - SCOPUS:69949098215
SN - 9781424425990
T3 - 2008 International SoC Design Conference, ISOCC 2008
SP - I379-I382
BT - 2008 International SoC Design Conference, ISOCC 2008
T2 - 2008 International SoC Design Conference, ISOCC 2008
Y2 - 24 November 2008 through 25 November 2008
ER -