TY - GEN
T1 - Scan chain swapping using TSVs for test power reduction in 3D-IC
AU - Lee, Ingeol
AU - Park, Jaeseok
AU - Kang, Sungho
PY - 2013
Y1 - 2013
N2 - Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.
AB - Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.
UR - http://www.scopus.com/inward/record.url?scp=84906897820&partnerID=8YFLogxK
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U2 - 10.1109/ISOCC.2013.6863963
DO - 10.1109/ISOCC.2013.6863963
M3 - Conference contribution
AN - SCOPUS:84906897820
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 170
EP - 171
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -