Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)


As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.

Original languageEnglish
Title of host publicationProceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781467397391
Publication statusPublished - 2015 Feb 28
Event24th IEEE Asian Test Symposium, ATS 2015 - Mumbai, Maharashtra, India
Duration: 2015 Nov 222015 Nov 25

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other24th IEEE Asian Test Symposium, ATS 2015
CityMumbai, Maharashtra

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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