As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.
|Title of host publication||Proceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|Publication status||Published - 2015 Feb 28|
|Event||24th IEEE Asian Test Symposium, ATS 2015 - Mumbai, Maharashtra, India|
Duration: 2015 Nov 22 → 2015 Nov 25
|Name||Proceedings of the Asian Test Symposium|
|Other||24th IEEE Asian Test Symposium, ATS 2015|
|Period||15/11/22 → 15/11/25|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering