Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

Sungyoul Seo; Yong Lee; Hyeonchan Lim; Joohwan Lee; Hongbom Yoo; Yojoung Kim; Sungho Kang

doi:10.1109/ATS.2015.8

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.

Original language	English
Title of host publication	Proceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015
Publisher	IEEE Computer Society
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781467397391
DOIs	https://doi.org/10.1109/ATS.2015.8
Publication status	Published - 2015 Feb 28
Event	24th IEEE Asian Test Symposium, ATS 2015 - Mumbai, Maharashtra, India Duration: 2015 Nov 22 → 2015 Nov 25

Publication series

Name	Proceedings of the Asian Test Symposium
Volume	2016-February
ISSN (Print)	1081-7735

Other

Other	24th IEEE Asian Test Symposium, ATS 2015
Country/Territory	India
City	Mumbai, Maharashtra
Period	15/11/22 → 15/11/25

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2015.8

Cite this

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title = "Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction",

abstract = "As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.",

author = "Sungyoul Seo and Yong Lee and Hyeonchan Lim and Joohwan Lee and Hongbom Yoo and Yojoung Kim and Sungho Kang",

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Seo, S, Lee, Y, Lim, H, Lee, J, Yoo, H, Kim, Y & Kang, S 2015, Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction. in Proceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015., 7422226, Proceedings of the Asian Test Symposium, vol. 2016-February, IEEE Computer Society, pp. 1-6, 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, Maharashtra, India, 15/11/22. https://doi.org/10.1109/ATS.2015.8

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction. / Seo, Sungyoul; Lee, Yong; Lim, Hyeonchan et al.
Proceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015. IEEE Computer Society, 2015. p. 1-6 7422226 (Proceedings of the Asian Test Symposium; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Seo, Sungyoul

AU - Lee, Yong

AU - Lim, Hyeonchan

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AU - Yoo, Hongbom

AU - Kim, Yojoung

AU - Kang, Sungho

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AB - As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.

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Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

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