Abstract
A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient design verification tool to reduce the overall design cycle time.
| Original language | English |
|---|---|
| Pages (from-to) | 197-200 |
| Number of pages | 4 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publication status | Published - 1996 |
| Event | Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: 1996 Sept 23 → 1996 Sept 27 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering