Resource utilization optimized design method for matched filter of pss searcher

Dohyun Kim; Taeyang Jeong; Eui Young Chung

doi:10.1109/ISOCC50952.2020.9333027

Resource utilization optimized design method for matched filter of pss searcher

Dohyun Kim, Taeyang Jeong, Eui Young Chung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	290-291
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333027
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This research was supported by R&D program for advanced integrated-intelligence for identification through the National Research Foundation of Korea(NRF) funded by Ministry of Trade, Industry and Energy (2018M3E3A1057248), And the chip fabrication and EDA Tool were supported by the IC Design Education Center.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9333027

Cite this

Kim, D., Jeong, T., & Chung, E. Y. (2020). Resource utilization optimized design method for matched filter of pss searcher. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 290-291). [9333027] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333027

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abstract = "In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.",

author = "Dohyun Kim and Taeyang Jeong and Chung, {Eui Young}",

note = "Funding Information: ACKNOWLEDGMENT This research was supported by R&D program for advanced integrated-intelligence for identification through the National Research Foundation of Korea(NRF) funded by Ministry of Trade, Industry and Energy (2018M3E3A1057248), And the chip fabrication and EDA Tool were supported by the IC Design Education Center. Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

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Kim, D, Jeong, T & Chung, EY 2020, Resource utilization optimized design method for matched filter of pss searcher. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333027, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 290-291, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333027

Resource utilization optimized design method for matched filter of pss searcher. / Kim, Dohyun; Jeong, Taeyang; Chung, Eui Young.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 290-291 9333027 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: ACKNOWLEDGMENT This research was supported by R&D program for advanced integrated-intelligence for identification through the National Research Foundation of Korea(NRF) funded by Ministry of Trade, Industry and Energy (2018M3E3A1057248), And the chip fabrication and EDA Tool were supported by the IC Design Education Center. Publisher Copyright: © 2020 IEEE.

PY - 2020/10/21

Y1 - 2020/10/21

N2 - In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.

AB - In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

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ER -

Resource utilization optimized design method for matched filter of pss searcher

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

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