Resource-efficient FPGA architecture of canny edge detector

Yunseok Jang; Junwon Mun; Jaeseok Kim

doi:10.1109/ISOCC.2016.7799796

Resource-efficient FPGA architecture of canny edge detector

Yunseok Jang, Junwon Mun, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	299-300
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799796
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. NRF-2015R1A2A2A01004883), and was also supported by IDEC(IPC, EDA Tool, MPW).

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799796

Cite this

Jang, Y., Mun, J., & Kim, J. (2016). Resource-efficient FPGA architecture of canny edge detector. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 299-300). Article 7799796 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799796

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abstract = "Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.",

author = "Yunseok Jang and Junwon Mun and Jaeseok Kim",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. NRF-2015R1A2A2A01004883), and was also supported by IDEC(IPC, EDA Tool, MPW). Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

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language = "English",

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Jang, Y, Mun, J & Kim, J 2016, Resource-efficient FPGA architecture of canny edge detector. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799796, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 299-300, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799796

Resource-efficient FPGA architecture of canny edge detector. / Jang, Yunseok; Mun, Junwon; Kim, Jaeseok.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 299-300 7799796 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. NRF-2015R1A2A2A01004883), and was also supported by IDEC(IPC, EDA Tool, MPW). Publisher Copyright: © 2016 IEEE.

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N2 - Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.

AB - Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.

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Resource-efficient FPGA architecture of canny edge detector

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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