Reconfigurable microarchitecture-based low power motion compensation for H.264/AVC

Introduction The demand of low-power and high-speed computing architecture for mobile systems has been increased dramatically due to the dominant popularity of multimedia and video processing. At the same time, with a fast growing VLSI technology, the architecture of digital integrated systems has evolved at a very fast pace. Thus, today’s chips can integrate several complex functions, memories, and logic on the same die, called system-on-chip (SoC), which allows designing multimedia systems within a short period. Furthermore, this technical evolution grows into SoC platform technology targeting a class of applications [1]. Mobile multimedia systems are mostly targeted for realtime applications based on computationally intensive video coding algorithms on limited storage capacity and bandwidth-constrained wireless networks. H.264/AVC [2], the latest international video coding standard, is the most remarkable codec at the present time since it can make highquality motion pictures transmitted at low bit rates, and defines three profiles: Baseline, Main, and Extended. The Baseline profile is the simplest profile; it targets mobile applications with limited processing resources such as digital multimedia broadcasting (DMB) [3] in Korea. TheMain profile is intended for digital television broadcasting and next-generation DVD applications by adding several features to improve video quality at the expense of increasing computational complexity greatly. The Extended profile targets streaming video possessing features to improve error resilience and to facilitate switching between different bitstreams.