TY - JOUR
T1 - REACT
T2 - Scalable and High-Performance Regular Expression Pattern Matching Accelerator for In-Storage Processing
AU - Jeong, Won Seob
AU - Lee, Changmin
AU - Kim, Keunsoo
AU - Yoon, Myung Kuk
AU - Jeon, Won
AU - Jung, Myoungsoo
AU - Ro, Won Woo
N1 - Publisher Copyright:
© 1990-2012 IEEE.
PY - 2020/5/1
Y1 - 2020/5/1
N2 - This article proposes REACT, a regular expression matching accelerator, which can be embedded in a modern Solid-State Drive (SSD) and a novel data access scheduling algorithm for high matching throughput. Specifically, REACT, including our data access scheduling algorithm, increases the utilization of SSD and the degree of internal memory parallelism for pattern matching processes. While the low-level flash exhibits long latency, modern SSDs in practice achieve high I/O performance by utilizing the massive internal parallelism at the system-level. However, exploiting the parallelism is limited for pattern matching since the sub-blocks, which constitute an input data and can be placed in multiple flash pages, should be tested in a sequence to process the input correctly. This limitation can induce low utilization of the accelerator. To address this challenge, the proposed REACT simultaneously processes multiple input streams with a parallel processing architecture to maximize matching throughput by hiding the long and irregular latency. The scheduling algorithm finds a data stream which requires a sub-block in closest time and prioritizes the access request to reduce the data stall of REACT. REACT achieves maximum 22.6 percent of matching throughput improvement on a 16-channel high-performance SSD compared to the accelerator without the proposed scheduling algorithm.
AB - This article proposes REACT, a regular expression matching accelerator, which can be embedded in a modern Solid-State Drive (SSD) and a novel data access scheduling algorithm for high matching throughput. Specifically, REACT, including our data access scheduling algorithm, increases the utilization of SSD and the degree of internal memory parallelism for pattern matching processes. While the low-level flash exhibits long latency, modern SSDs in practice achieve high I/O performance by utilizing the massive internal parallelism at the system-level. However, exploiting the parallelism is limited for pattern matching since the sub-blocks, which constitute an input data and can be placed in multiple flash pages, should be tested in a sequence to process the input correctly. This limitation can induce low utilization of the accelerator. To address this challenge, the proposed REACT simultaneously processes multiple input streams with a parallel processing architecture to maximize matching throughput by hiding the long and irregular latency. The scheduling algorithm finds a data stream which requires a sub-block in closest time and prioritizes the access request to reduce the data stall of REACT. REACT achieves maximum 22.6 percent of matching throughput improvement on a 16-channel high-performance SSD compared to the accelerator without the proposed scheduling algorithm.
KW - In-storage processing (ISP)
KW - accelerator
KW - regular expression matching
KW - solid-state drive
UR - http://www.scopus.com/inward/record.url?scp=85078494155&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85078494155&partnerID=8YFLogxK
U2 - 10.1109/TPDS.2019.2953646
DO - 10.1109/TPDS.2019.2953646
M3 - Article
AN - SCOPUS:85078494155
SN - 1045-9219
VL - 31
SP - 1137
EP - 1151
JO - IEEE Transactions on Parallel and Distributed Systems
JF - IEEE Transactions on Parallel and Distributed Systems
IS - 5
M1 - 8901167
ER -