The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.
All Science Journal Classification (ASJC) codes
- General Engineering
- General Physics and Astronomy