Pulsed PMOS sense amplifier for high speed single-ended SRAM

Juhyun Park; Hanwool Jeong; Seong Ook Jung

doi:10.23919/ELINFOCOM.2018.8330662

Pulsed PMOS sense amplifier for high speed single-ended SRAM

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

Original language	English
Title of host publication	International Conference on Electronics, Information and Communication, ICEIC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538647547
DOIs	https://doi.org/10.23919/ELINFOCOM.2018.8330662
Publication status	Published - 2018 Apr 2
Event	17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States Duration: 2018 Jan 24 → 2018 Jan 27

Publication series

Name	International Conference on Electronics, Information and Communication, ICEIC 2018
Volume	2018-January

Other

Other	17th International Conference on Electronics, Information and Communication, ICEIC 2018
Country/Territory	United States
City	Honolulu
Period	18/1/24 → 18/1/27

Bibliographical note

Publisher Copyright:
© 2018 Institute of Electronics and Information Engineers.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Information Systems
Computer Networks and Communications
Computer Science Applications
Signal Processing
Electrical and Electronic Engineering

Access to Document

10.23919/ELINFOCOM.2018.8330662

Cite this

Park, J., Jeong, H., & Jung, S. O. (2018). Pulsed PMOS sense amplifier for high speed single-ended SRAM. In International Conference on Electronics, Information and Communication, ICEIC 2018 (pp. 1-4). (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2018.8330662

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title = "Pulsed PMOS sense amplifier for high speed single-ended SRAM",

abstract = "In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80\% compared with conventional domino logic and reduces energy consumption by 40\% compared with previously proposed pseudo nMOS based sense amplifier.",

keywords = "8T SRAM, sense amplifier, single-ended read operation",

author = "Juhyun Park and Hanwool Jeong and Jung, \{Seong Ook\}",

note = "Publisher Copyright: {\textcopyright} 2018 Institute of Electronics and Information Engineers.; 17th International Conference on Electronics, Information and Communication, ICEIC 2018 ; Conference date: 24-01-2018 Through 27-01-2018",

year = "2018",

month = apr,

day = "2",

doi = "10.23919/ELINFOCOM.2018.8330662",

language = "English",

series = "International Conference on Electronics, Information and Communication, ICEIC 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Park, J, Jeong, H & Jung, SO 2018, Pulsed PMOS sense amplifier for high speed single-ended SRAM. in International Conference on Electronics, Information and Communication, ICEIC 2018. International Conference on Electronics, Information and Communication, ICEIC 2018, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 17th International Conference on Electronics, Information and Communication, ICEIC 2018, Honolulu, United States, 18/1/24. https://doi.org/10.23919/ELINFOCOM.2018.8330662

Pulsed PMOS sense amplifier for high speed single-ended SRAM. / Park, Juhyun; Jeong, Hanwool ; Jung, Seong Ook.
International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Pulsed PMOS sense amplifier for high speed single-ended SRAM

AU - Park, Juhyun

AU - Jeong, Hanwool

AU - Jung, Seong Ook

PY - 2018/4/2

Y1 - 2018/4/2

N2 - In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

AB - In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

KW - 8T SRAM

KW - sense amplifier

KW - single-ended read operation

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M3 - Conference contribution

AN - SCOPUS:85048485725

T3 - International Conference on Electronics, Information and Communication, ICEIC 2018

SP - 1

EP - 4

BT - International Conference on Electronics, Information and Communication, ICEIC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International Conference on Electronics, Information and Communication, ICEIC 2018

Y2 - 24 January 2018 through 27 January 2018

ER -

Pulsed PMOS sense amplifier for high speed single-ended SRAM

Abstract

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Bibliographical note

UN SDGs

All Science Journal Classification (ASJC) codes

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