TY - GEN
T1 - Process variation-aware floorplanning for 3D many-core processors
AU - Hong, Hyejeong
AU - Lim, Jaeil
AU - Kang, Sungho
PY - 2012
Y1 - 2012
N2 - Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
AB - Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
UR - http://www.scopus.com/inward/record.url?scp=84875524635&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84875524635&partnerID=8YFLogxK
U2 - 10.1109/EDAPS.2012.6469421
DO - 10.1109/EDAPS.2012.6469421
M3 - Conference contribution
AN - SCOPUS:84875524635
SN - 9781467314435
T3 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
SP - 193
EP - 196
BT - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
T2 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Y2 - 9 December 2012 through 11 December 2012
ER -