Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

Tae Woo Oh, Hanwool Jeong, Juhyun Park, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for near-threshold operation is proposed. In previous local bit-line sharing SRAMs, such as average-8T and full-swing local bit-line (FSLB) SRAMs, multiple bit-cells share a local bit-line pair with a small capacitance for high read stability. However, the average-8T SRAM has a considerably large delay because the full development of the local bit-line cannot be achieved. On the other hand, the FSLB SRAM reduces the delay but requires a timing constraint of control signals to achieve sufficient read sensing margin. The proposed PCLBS SRAM achieves high read speed by fully developing local bit-line pair without a timing constraint. Furthermore, the proposed PCLBS SRAM enhances the read stability and the write ability by, respectively, applying a pre-charged local bit-line scheme and transmission gates in write paths. Based on a 22-nm FinFET technology, the FSLB and proposed PCLBS SRAM have the minimum operating voltages of 0.44 and 0.4 V, respectively, while achieving the σ target read stability and write ability yields. Compared with the FSLB SRAM, the proposed PCLBS SRAM consumes 21% less energy at each minimum operating voltage and has 57% smaller read delay at the operating voltage of 0.4 V.

Original languageEnglish
Article number7932141
Pages (from-to)2737-2747
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number10
Publication statusPublished - 2017 Oct

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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