@inproceedings{14b4ff40af4940ef93f29f982f01e619,
title = "Practice and experience of an embedded processor core modeling",
abstract = "This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).",
author = "Park, {Gi Ho} and Sung, {Woo Chung} and Kim, {Han Jong} and Im, {Jung Bin} and Park, {Jung Wook} and Kim, {Shin Dug} and Park, {Sung Bae}",
year = "2006",
doi = "10.1007/11847366_64",
language = "English",
isbn = "3540393684",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "621--630",
booktitle = "High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings",
address = "Germany",
note = "2nd International Conference on High Performance Computing and Communications, HPCC 2006 ; Conference date: 13-09-2006 Through 15-09-2006",
}