POSTER: Location-Aware Computation Mapping for Manycore Processors

Orhan Kislal; Jagadish Kotra; Xulong Tang; Mahmut Taylan Kandemir; Myoungsoo Jung

doi:10.1109/PACT.2017.20

POSTER: Location-Aware Computation Mapping for Manycore Processors

Orhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Employing an on-chip network in a manycore system (to improve scalability) makes the latencies of data accesses issued by a core non-uniform, which significant impact application performance. This paper presents a compiler strategy which involves exposing architecture information to the compiler to enable optimized computation-to-core mapping. Our scheme takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. Our experiments of 12 multi-threaded applications reveal that, on average, our approach reduces the on-chip network latency in a 6x6 manycore system by 49.5% in the case of private LLCs and 52.7% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 14.8% and 15.2% for the private LLC and shared LLC based systems.

Original language	English
Title of host publication	Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	138-139
Number of pages	2
ISBN (Electronic)	9781467395243
DOIs	https://doi.org/10.1109/PACT.2017.20
Publication status	Published - 2017 Oct 31
Event	26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 - Portland, United States Duration: 2017 Sept 9 → 2017 Sept 13

Publication series

Name	Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume	2017-September
ISSN (Print)	1089-795X

Other

Other	26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
Country/Territory	United States
City	Portland
Period	17/9/9 → 17/9/13

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Software
Theoretical Computer Science
Hardware and Architecture

Access to Document

10.1109/PACT.2017.20

Cite this

Kislal, O., Kotra, J., Tang, X., Kandemir, M. T., & Jung, M. (2017). POSTER: Location-Aware Computation Mapping for Manycore Processors. In Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 (pp. 138-139). (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT; Vol. 2017-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PACT.2017.20

Kislal, Orhan ; Kotra, Jagadish ; Tang, Xulong et al. / POSTER : Location-Aware Computation Mapping for Manycore Processors. Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 138-139 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).

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abstract = "Employing an on-chip network in a manycore system (to improve scalability) makes the latencies of data accesses issued by a core non-uniform, which significant impact application performance. This paper presents a compiler strategy which involves exposing architecture information to the compiler to enable optimized computation-to-core mapping. Our scheme takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. Our experiments of 12 multi-threaded applications reveal that, on average, our approach reduces the on-chip network latency in a 6x6 manycore system by 49.5% in the case of private LLCs and 52.7% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 14.8% and 15.2% for the private LLC and shared LLC based systems.",

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Kislal, O, Kotra, J, Tang, X, Kandemir, MT & Jung, M 2017, POSTER: Location-Aware Computation Mapping for Manycore Processors. in Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, vol. 2017-September, Institute of Electrical and Electronics Engineers Inc., pp. 138-139, 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, United States, 17/9/9. https://doi.org/10.1109/PACT.2017.20

POSTER: Location-Aware Computation Mapping for Manycore Processors. / Kislal, Orhan; Kotra, Jagadish; Tang, Xulong et al.
Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 138-139 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT; Vol. 2017-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Kislal O, Kotra J, Tang X, Kandemir MT, Jung M. POSTER: Location-Aware Computation Mapping for Manycore Processors. In Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 138-139. (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). doi: 10.1109/PACT.2017.20

POSTER: Location-Aware Computation Mapping for Manycore Processors

Abstract

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