Abstract
In this paper, we proposed parasitic capacitance prediction methodology using Bayesian optimization to accelerate the iterative design process. The layout process while circuit design is inevitable since the effect of parasitic RC after layout increases as technology scaled down. However, the layout process consumes many time and human resources. To overcome this problem, we present Bayesian optimization based parasitic capacitance estimation methodology with parasitic capacitance modelling. Our proposed methodology can predict the parasitic capacitance of various inverter and NAND2 with less than 3.1% of error.
| Original language | English |
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| Title of host publication | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350371888 |
| DOIs | |
| Publication status | Published - 2024 |
| Event | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 - Taipei, Taiwan, Province of China Duration: 2024 Jan 28 → 2024 Jan 31 |
Publication series
| Name | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
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Conference
| Conference | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
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| Country/Territory | Taiwan, Province of China |
| City | Taipei |
| Period | 24/1/28 → 24/1/31 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Computer Science Applications
- Hardware and Architecture
- Information Systems
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering